The invention relates to a DRAM cell arrangement and a method for fabricating it.
Generally endeavors are made to produce a DRAM cell arrangement with an ever higher packing density. For a DRAM cell arrangement in which the information is stored in the form of a charge on a storage capacitor, the problem arises of producing the storage capacitor on a small area but nonetheless providing it with a sufficiently high capacitance in order that the signal of the charge is not submerged in background noise when the information is read out.
K. Hoffmann, xe2x80x9cVLSI-Entwurf: Modelle und Schaltungen [VLSI Design: Models and Circuits]xe2x80x9d (1996), pages 411 to 415 describes a DRAM cell arrangement having so-called folded bit lines. On account of comparable bulk resistances and coupling capacitances, the background noise of bit lines which are arranged close together is similar. In a DRAM cell arrangement having folded bit lines, the signal of a bit line which is connected to a storage capacitor to be read is compared with a signal of an adjacent bit line, which only comprises the background noise. Since the two bit lines are adjacent to one another, part of the background noise can thus be filtered out. Consequently, such a differential reading method makes it possible to read out a smaller charge, which produces a smaller voltage change on the bit line. A minimum capacitance of the storage capacitor required for reading out the information is smaller than in the case of a DRAM cell arrangement having so-called open bit lines, i.e. without folded bit lines. A word line which addresses the memory cell to be read must not be connected to any memory cell connected to the adjacent bit line, in order that the signal of the adjacent bit line only comprises background noise. In the case of the DRAM cell arrangement described, a memory cell comprises a transistor and a storage capacitor, which are arranged next to one another. A first word line and a second word line are arranged above the memory cell. Mutually adjacent memory cells along the word lines are alternately connected to the first word line and the second word line. To that end, the transistors and the storage capacitors of the memory cells are arranged in such a way that a transistor and a storage capacitor of different memory cells are alternately arranged next to one another along the word lines. The bit lines run transversely with respect to the word lines.
T. Ozaki et al., xe2x80x9c0.228 xcexcm2 Trench Cell Technologies with Bottle-Shaped Capacitor for 1 Giga-Bit DRAMs,xe2x80x9d IEDM (1995) 661, describes a DRAM cell arrangement having open bit lines. A memory cell comprises a planar transistor and a storage capacitor connected in series therewith. Two planar transistors having a common source/drain region are arranged between two respective storage capacitors whose storage nodes are arranged in depressions in a substrate. In order to increase the capacitance of the storage capacitor, firstly an upper region of the depression is produced, the sidewalls of which region are provided with an oxide. Afterward, the oxide is removed at the bottom of the depression and the depression is deepened further, thereby producing a lower region of the depression. The lower region of the depression is widened by a wet etching process, with the result that a cross section of the lower region of the depression is larger than a cross section of the upper region. By virtue of the widening of the lower region of the depression, the surface area of a capacitor dielectric which covers areas of the depression is enlarged, and the capacitance of the storage capacitor is thus increased.
EP 0 852 396 describes a DRAM cell arrangement in which, in order to increase the packing density, a transistor of a memory cell is arranged above a storage capacitor of the memory cell. Active regions of the memory cells are in each case surrounded by an insulating structure arranged in a substrate. A depression is produced in the substrate for each memory cell, a storage node of the storage capacitor being arranged in the lower region of the depression and a gate electrode of the transistor being arranged in the upper region of the depression. An upper source/drain region, a channel region and a lower source/drain region of the transistor are arranged one above the other in the substrate. The lower source/drain region is connected to the storage node at a first sidewall of the depression. The insulating structure adjoins a second sidewall, opposite to the first sidewall, of the depression, with the result that the storage node does not adjoin the substrate there. A capacitor electrode of the storage capacitor is formed by the ad diffusion of dopant into the substrate. As in the publication by T. Ozaki et al. (see above), a lower region of the depression is widened in this case, too. A bit line adjoins the upper source/drain region and runs above the substrate. The gate electrode is insulated from the substrate and from the bit lines by a gate dielectric and the insulating structure. The gate electrode adjoins a word line running above the bit line.
The invention is based on the problem of specifying a DRAM cell arrangement which has folded bit lines, whose word lines and bit lines can be produced with high electrical conductivity and which can, at the same time, be fabricated with a high packing density. Furthermore, the intention is to specify a method for fabricating it.
The problem is solved by means of a DRAM cell arrangement in which memory cells are arranged in columns which run parallel to a y-axis and rows which run parallel to an x-axis, in a substrate. The memory cells of a column are connected to a bit line which runs above a main area of the substrate. The memory cells of a row are alternately connected to a first word line and a second word line. Furthermore the memory cells each comprise a pillar-shaped connection structure. First parts of the first word line are each arranged offset in the y-direction, i.e. in the positive direction along the y-axis, with respect to one of the connection structures of the memory cells to which the first word line is connected, with the result that this connection structure is overlapped from above but not covered. A second part of the first word line is strip-shaped, runs above the main area and essentially parallel to the x-axis and adjoins the first parts of the first word line from above. Sidewalls of the first word line are provided with insulating spacers. First parts of the second word line are arranged between the spacers of mutually adjacent first word lines of the memory cells. The first parts of the second word line are each arranged offset oppositely to the y-direction, i.e. in the negative direction along the y-axis, with respect to one of the connection structures of the memory cells to which the second word line is connected, with the result that this connection structure is overlapped from above but not covered. A second part of the second word line is strip-shaped, runs above the main area and essentially parallel to the x-axis, adjoins the first parts of the second word line from above and is arranged above the first word line and the bit line. The first word line and the second word line overlap the row.
The problem is furthermore solved by means of a method for fabricating a DRAM cell arrangement, in which memory cells are produced in columns which run parallel to a y-axis and rows which run parallel to an x-axis. A pillar-shaped connection structure is in each case produced for the memory cells. Bit lines are produced which are respectively connected to the memory cells of a column. A first insulating layer is applied over the connection structures of memory cells. First contact holes are produced in the first insulating layer, which uncover parts of each second connection structure of the memory cells of a row in such a way that the first contact holes are arranged offset in the y-direction with respect to the connection structures. Conductive material is deposited, with the result that the first contact holes are filled with first parts of first word lines. A second insulating layer is deposited. The conductive material and the second insulating layer are patterned, thereby producing strip-shaped second parts of the first word lines, which run essentially parallel to the x-axis, adjoin the first parts of the first word line from above and are covered by the second insulating layer. Sidewalls of the first word lines are provided with insulating spacers. The first insulating layer is etched selectively with respect to the second insulating layer and the spacers, with the result that parts of the remaining connection structures are uncovered in such a way that second contact holes are produced, which are arranged offset oppositely to the y-direction with respect to the connection structures. Conductive material is deposited, with the result that the second contact holes are filled with first parts of second word lines, which are arranged between the spacers of mutually adjacent first word lines. The conductive material is patterned, thereby producing strip-shaped second parts of the second word lines, which run essentially parallel to the x-axis, adjoin the first parts of the second word lines from above and are arranged above the first word lines and the bit lines.
Materials having high electrical conductivities, such as e.g. WSi, TiSi, MoSi, CoSi, TaSi, are preferably deposited above a semiconductor substrate since, on the one hand, they cover edges formed e.g. by depressions in the semiconductor substrate poorly, i.e. non-uniformly, and, on the other hand, they should be arranged at a distance from the semiconductor substrate in order to avoid contamination of the semiconductor substrate. Moreover, mechanical strain or damage, caused by the deposition, of a surface of the substrate is thereby avoided. Since both the bit lines and the second parts of the first word lines and of the second word lines run above the substrate, they can contain materials having high electrical conductivities. Furthermore, the bit lines and the word lines can be produced at the same time as gate electrodes of transistors of a periphery of the DRAM cell arrangement by patterning a layer or a layer sequence made of conductive materials with the aid of a mask by means of etching. In this case, the bit lines and the word lines have a so-called planar construction.
Since the memory cells of a row are alternately connected to the first word line and the second word line, and the bit lines in each case connect the memory cells of a column to one another, there are no two memory cells which are connected to mutually adjacent bit lines and are simultaneously connected to the same word line. The DRAM cell arrangement consequently has folded bit lines.
The DRAM cell arrangement can have a high packing density since only the spacers, which can be fabricated with thin horizontal cross sections, i.e. cross sections parallel to the main area, laterally isolate the first word lines from the second word lines.
The bit lines and the word lines can be produced after the fabrication of the memory cells. This is advantageous since the production of the bit lines and word lines from metals is made possible, after the application of which process steps at high temperatures, which can lead for example to the contamination of other parts of the DRAM cell arrangement, are avoided. By way of example, a layer sequence comprising Ti, TiN and W can be patterned for the purpose of producing the word lines and the bit lines.
The production of the word lines is insensitive to alignment inaccuracies with regard to the connection structures. The extensive self-aligned contact-connection of the connection structures by the word lines enables the DRAM cell arrangement to have a high packing density. The alignment of photoresist masks for producing the first word lines and the second word lines merely has to guarantee that the connection structures are partially overlapped, since etching is effected selectively with respect to the spacers and the second insulating layer during the production of the second word lines, with the result that contact holes for the second word lines cannot be produced in and adjoining the first word lines. The alignment inaccuracy preferably amounts to up to a third of the width of the connection structures.
On account of the insensitivity to alignment inaccuracies, the DRAM cell arrangement can be produced with a high packing density. The first word lines preferably have a width equal to the minimum feature size F that can be fabricated in the technology used for fabricating the DRAM cell arrangement. The same applies to the second word lines, to distances between mutually adjacent first word lines, to distances between mutually adjacent second word lines and to the widths of the connection structures. The bit lines can likewise have a width and distances from one another which amount to F. Accordingly, in a plan view of the DRAM cell arrangement, the first word lines and the second word lines can be arranged alternately without a spacing directly next to one another or in an overlapping manner. The memory cell can be fabricated with an area of 4F2.
The connection structures can project above the main area of the substrate. In this case, sidewalls of the connection structures are provided with further insulating spacers between which first parts of the bit lines adjoin. Second parts of the bit lines are arranged between the first parts of the bit lines and have a larger width than the first parts of the bit lines. The bit lines adjoin the main area and in each case run between connection structures which are adjacent to one another in the x-direction. This has the advantage that the bit lines can be produced in a largely self-aligned manner between the connection structures. To that end, an insulation is produced which surrounds the connection structures provided with the further spacers. With the aid of a strip-shaped mask whose strips run parallel to the columns and which each overlap connection structures of memory cells of a column, trenches are produced in the insulation, etching being effected selectively with respect to the spacers and the first insulating layer. Afterward, conductive material is deposited and removed until the insulation is uncovered, with the result that the bit lines are produced in the trenches, and that the bit lines not overlapping the connection structures. This is advantageous since otherwise the effective cross section of the connection structures would be reduced, which would in turn result in a reduction in the overlap of the connection structures with the word lines.
It lies within the scope of the invention for a memory cell to comprise a transistor and a storage capacitor connected in series therewith.
In order to increase the packing density, it is advantageous if the transistor is configured as a vertical transistor, with the result that an upper source/drain region is arranged above a channel region and the channel region is arranged above a lower source/drain region of the transistor.
In order to further increase the packing density, it is advantageous if the transistor and the storage capacitor are arranged one above the other.
It lies within the scope of the invention for the upper source/drain region to be connected to the bit line. The connection structure is connected to a gate electrode of the transistor.
A depression may be provided for the memory cell in the substrate, a storage node of the storage capacitor being arranged in the lower region of the depression and the connection structure being arranged in the upper region of the depression. Areas of the lower region of the depression are provided with a capacitor dielectric. The storage node is electrically insulated from the connection structure. In the upper region of the depression, at least a first sidewall of the depression is provided with a gate dielectric. A part of the connection structure is arranged at least on the first sidewall and can act as a gate electrode of the transistor. The upper source/drain region is arranged on the main area of the substrate and adjoins two depressions that are adjacent to one another in the x-direction.
In order to produce such a DRAM cell arrangement, after the application of a capacitor dielectric, the depressions are filled with conductive material up to a middle height. To that end, the conductive material can be deposited, planarized by chemical mechanical polishing and then etched back as far as the middle height. Afterward, uncovered parts of the capacitor dielectric are removed, with the result that areas of the depressions are provided with the capacitor dielectric only up to the middle height. Afterward, the depressions are filled further by conductive material up to an upper height, which is situated in the lower region, with the result that the conductive material adjoins the substrate between the middle height and the upper height. The conductive material in the depressions forms the storage nodes. A gate dielectric is produced in such a way that it covers the storage node. As an alternative, firstly insulating material is applied to the storage node and the gate dielectric is grown subsequently. The connection structure is then produced in the upper region of the depression. The gate dielectric or the insulating material isolates the connection structure from the storage node.
It lies within the scope of the invention for the depression to be produced in a layer sequence, with the result that the lower source/drain region, the channel region and the upper source/drain region are produced from layers of the layer sequence.
The lower source/drain region is preferably produced by dopant diffusing from the storage node Abetween the upper height and the middle height into the substrate by means of a heat-treatment step. As a result, the lower source/drain region only adjoins a depression, with the result that channel regions of different transistors are electrically connected to one another. This is advantageous since floating body effects are avoided in this way.
It is advantageous to apply a mask prior to the removal of the uncovered parts of the capacitor dielectric above the middle height, which mask covers second sidewalls, opposite to the first sidewalls, of the depressions. As a result, the capacitor dielectric is preserved on the second sidewall, with the result that the storage node adjoins the substrate only at the first sidewall between the middle height and the upper height. The distance between the second sidewall and the first sidewall of mutually adjacent depressions can be reduced in this case without leakage currents arising between the associated storage nodes. The packing density of the DRAM cell arrangement can thus be increased. After the production of the storage nodes, uncovered parts of the capacitor dielectric which are arranged on the second sidewalls above the upper height can be removed.
The upper source/drain region can be produced by patterning a doped layer of the substrate, the layer adjoining the main area. The patterning is effected on the one hand by the production of the depressions. On the other hand, isolating structures are produced between upper source/drain regions that are adjacent to one another in the y-direction. The isolating structures can be produced by producing further trenches in the substrate, which run parallel to the rows and are arranged between the depressions. The further trenches are subsequently filled with insulating material.
The upper source/drain region can alternatively be produced by carrying out an implantation after the production of the depressions and isolating structures.
The depressions can be produced in a self-aligned manner between the isolating structures by producing the isolating structures and then etching the substrate with the aid of a strip-shaped mask selectively with respect to the isolating structures, strips of the mask running transversely with respect to the isolating structures.
In order to prevent a gate electrode of a depression from driving a transistor of the adjacent depression, it is advantageous if insulating structures which are thicker than the gate dielectric are arranged on the second sidewalls of the depressions. In order to increase the packing density, it is advantageous here if the insulating structures are arranged in the upper regions of the depressions instead of in the substrate. In order to produce the insulating structures, firstly the connection structures may be produced by producing the gate dielectric and then depositing conductive material and patterning it with the aid of a mask which covers the second sidewalls of the depressions. The connection structures are arranged on the first sidewalls of the depressions and do not completely fill the depressions. The insulating structures are produced by depositing insulating material and etching it back.
It is advantageous if the capacitor dielectric has a first part, which covers areas of the lower regions of the depressions up to a lower height, which lies below the middle height, and a second part, which is thicker than the first part and covers areas of the depressions between the lower height and the middle height. Depending on the conductivity types chosen, a pnp junction or an npn junction is formed by the lower source/drain region, the substrate and the capacitor electrode, which junction, driven by the storage node, can cause leakage currents. Thus, if the capacitor dielectric is particularly thick between the capacitor electrode and the second source/drain region, the storage node no longer drives the junction and leakage currents are avoided. To that end, after the production of the depressions, the first part of the capacitor dielectric is applied over the whole area. The depressions are filled by conductive material up to a lower height, which lies below the middle height. Uncovered parts of the first part of the capacitor dielectric are subsequently removed. The second part of the capacitor dielectric is firstly applied over the whole area and removed by anisotropic etching from a surface of the conductive material. The depression is filled further by the deposition of conductive material up to the middle height. The procedure may then continue in the manner described above.
A capacitor electrode of the capacitor is arranged in the substrate and adjoins the capacitor dielectric. The capacitor electrode may be configured as a doped substrate layer common to all of the capacitors. The doped layer may be produced e.g. by epitaxy or implantation prior to the production of the memory cells. As an alternative, a dopant source is introduced in the depressions, from which source dopant diffuses into the substrate, and forms the doped layer there, in a heat-treatment step.
The dopant source is e.g. arsenic glass. After the production of the depressions, the arsenic glass is deposited, with the result that areas of the depressions are covered. The lower regions of the depressions provided with the arsenic glass are filled with e.g. photoresist. Uncovered arsenic glass is subsequently removed. It is advantageous to grow a protective oxide after the removal of the photoresist. The protective oxide prevents arsenic from evaporating during the subsequent heat-treatment step during which arsenic diffuses from the arsenic glass into the substrate. The capacitor electrode is produced as an arsenic-doped part of the substrate which surrounds the lower regions of the depressions.
It is advantageous if the first sidewall is plane in the upper region and the area of the lower region is curved. The growth of the gate dielectric produced by thermal oxidation depends on the orientation of the first sidewall relative to the crystal structure of the substrate. If the first sidewall is plane, the gate dielectric can grow homogeneously since a plane area, in contrast to a curved area, has a defined orientation relative to the crystal structure. Control characteristics of the transistor in which the gate dielectric has a homogeneous thickness correspond to those of conventional planar transistors and have a particularly high subthreshold transconductance. If a part of the capacitor dielectric is grown by thermal oxidation on an area having an edge, the oxide turns out to be particularly thin on the edge. It is therefore possible for leakage currents to arise in the region of the edge. Therefore, it is advantageous if the capacitor dielectric is produced on an area having no edges. Even if the capacitor dielectric is produced by depositing material, edges in the area have a disadvantageous effect since field distortions occur at the edges and can reduce the breakdown voltage of the capacitor.
It lies within the scope of the invention for the upper region to have an essentially rectangular cross section which is larger than a cross section of the lower region, which is essentially circular or elliptic. To that end, after the production of the upper regions of the depression, auxiliary spacers are produced on the depressions by depositing material and anisotropically etching it back. The auxiliary spacers are rounded by an isotropic etching process, with the result that uncovered parts of bottoms of the depressions have a circumference without corners. The lower regions of the depressions are subsequently produced by anisotropic etching selectively with respect to the auxiliary spacers.
In order to increase the capacitance of the storage capacitor, it is advantageous if the lower region of the depression is subsequently extended by isotropically etching the substrate, with the result that its cross section is enlarged. This enlarges the area of the lower region on which the capacitor dielectric is arranged, with the result that the capacitance of the storage capacitor is increased.
A method is described below which prevents the situation where, on account of the finite selectivity of etching processes, an upper area of the isolating structures lies below the main area after the production of the depressions. Prior to the production of the isolating structures, a lower layer made of a first material is applied on the main area and an upper layer made of a second material is applied over the lower layer. The isolating structures are subsequently produced, the first material being used to fill the further trenches. An upper area of the isolating structures lies above the main area but below an upper area of the lower layer. By depositing and planarizing the second material until the lower layer is uncovered, auxiliary structures made of the second material are produced above the isolating structures. Afterward, the depressions are produced with the aid of the strip-shaped mask by firstly etching the first material selectively with respect to the second material, with the result that the upper area of the isolating structures lies above the main area in an unchanged manner, since the auxiliary structures protect the isolating structures. The depressions can subsequently be produced by etching uncovered parts of the substrate, the isolating structures and the lower layer serving as mask. In this case, on account of the finite selectivity of the etching process, the isolating structures and the lower layer are removed whose upper areas do not lie below the main area on account of the sufficient thickness of the lower layer after the production of the depressions.
The substrate may contain silicon and/or germanium and is preferably monocrystalline in order that the gate dielectric can be produced by thermal oxidation.
The bit lines and the word lines may be constructed in a multilayer manner. By way of example, it is possible to provide in each case a lower layer made of doped polysilicon and, above that, a layer made of a material having better electrical conductivity, e.g. silicide or metal.
An exemplary embodiment of the invention is explained in more detail below with reference to the figures.